THIN but Great Silicon 2 Design Objects


State-of-the-art of advanced CMOS technologies

In “Economic impact of the technology choices at 28nm/20nm” by H. Jones, IBS showed that 22/20nm node, the cost per function will not be lowered by using a conventional transistor shrink technique. The complexity/variability and the impossibility to reduce the effective gate length will cause the cost per gate to increase by 1.6%. This new trend in semiconductors could have a strong impact on the economy in Europe. Thus, traditional bulk-CMOS is coming to its end of life. New generation of CMOS processes with fully depleted transistor architectures will drive the next semiconductor era. A fully depleted transistor can be planar (FD-SOI) or tri-dimensional (finFET).


The finFET is a transistor design first developed at Berkeley University. It attempts to overcome the worst types of short-channel effect encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL). There are a number of subtly different forms of tri-dimensional transistor structures that are being described as finFETs. As shown in the next Figure, the architecture typically takes advantage of self-aligned process steps to produce extremely narrow features that are much smaller than the wavelength of light generally used to pattern devices on a silicon wafer.


It is possible to create very thin fins on the surface of a silicon wafer using selective-etching
processes, although they typically cannot currently be made less than 20nm to 30nm
because of the limits of lithographic resolution. The fin is used to form the raised channel.
The gate is then deposited so that it wraps around the fin to form the tri-gate structure. As the channel is extremely thin the gate has much greater control over the carriers within it, but when the device is switched on, the shape limits the current through it to a low level. So, multiple fins are used in parallel to provide higher drive strengths. Originally, the finFET was developed for use on silicon-on-insulator (SOI) wafers. Recent developments have made it possible to produce working finFETs on bulk silicon wafers and improve the performance of certain parameters. The steep doping profile used to control leakage into the bulk substrate has a beneficial impact on DIBL, although increased doping has a negative impact on variability.


Fully-Depleted Silicon On Insulator, FD-SOI, is emerging as a promising solution to continue the CMOS scaling roadmap at the 22nm technology node and beyond, especially for Low Power and System-on-Chip applications. Modern FD-SOI structures are considered for the 22/20nm node and beyond. As depicted in the next Figure, it relies on a silicon layer as thin as 5 to 8nm at fabricated device level (UTSOI, Ultra-Thin SOI) over a Buried Oxide (BOx). Transistors built into this top silicon layer are Ultra-Thin Body devices and have unique, extremely attractive characteristics. Two flavors of buried oxide can be used: standard thickness (typically 145nm thick as classically in volume production PD-SOI digital chips today), or ultra-thin BOx, for example 10 or 25nm (UTBOx, Ultra-Thin Buried Oxide). FD-SOI solves, with less process complexity, scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm.



FD-SOI is a 2D technology that allows transistors to run at frequencies up to 30%
faster than bulk CMOS, while being 50% more power efficient with lower leakage and a
much wider range of operation points down to lower voltages. For example, the same
ARM Cortex A9 processor can run at 150MHz at 0.6V in 28nm Low Power bulk technology and up to 800MHz in 28nm FD-SOI with body biasing. The current semiconductor roadmap promises a 40% increase in performance from 28nm FD-SOI to 14 nm FD-SOISOI (2014) and more than a 30% performance increase from 14nm to 10nm FD-SOISOI (2016).


FD-SOI also exhibits a radiation resistance in terms of single-event-upset (SEU)
resistance and current FD-SOI technologies are promising for fabricating low-cost
ASICs for advanced space systems.

The research leading to these results has received funding from the European Community under the ENIAC Nanoelectronics Framework Programme